The present invention relates to a memory apparatus for a disaster preventing system which is designed to serve as an interface apparatus to aid the processing by a computer of the alarm signals from an alarm system.
With a known type of alarm system designed to generate an alarm signal containing as its signal content a class of alarm, e.g., a fire, burglary or absence alarm or the location of an alarm, there are cases where the receiver of the alarm system is connected to a computer through an interface unit, whereby each alarm signal is subjected to data processing in the computer so as to give the necessary leading direction to a safe place, control the operation of various disaster preventive equipment such as fire screens, fire extinguishing equipment, etc. In this case, while the use of the ordinary interface unit will result in no difficult problems if the computer is for exclusive use with the alarm system, there are many instances where the computer is designed for economical reason or the like to control the operation of many different apparatus other than the alarm system, thus giving rise to the following disadvantages.
For example, where the centralized traffic control is accomplished by a large computer installed in a control building and the computer is operatively associated with the fire alarm system of the building, the control of train operation is given preference to the processing of alarm signals from the fire alarm system and consequently the computer is not allowed to work continuously on those alarm signals over a long period of time. As a result, with the alarm signals whose signal contents differ moment by moment, that is, the first signal differs from the second and so on, it is impossible to subject all the alarm signals to the data processing thus giving rise to a disadvantage that it is impossible to entirely grasp the course in which the fire has spreaded and it is thus impossible to give the proper leading direction to a safe place and effectively control the operation of the disaster preventing equipment.
While a memory circuit for temporarily storing alarm signals may be provided to overcome these deficiencies, this attempt of simply providing the memory circuit has the following disadvantages. In other words, the interface unit is so constructed that when a first alarm signal is generated so that the alarm signal is stored in the memory circuit and simultaneously an interruption signal is applied to the computer causing it to read the content of the memory circuit when it is idle, and consequently even in cases where the memory circuit contains only a single alarm signal the computer is required to read all the bits corresponding to the entire memory capacity of the memory circuit, thus wasting the read time. The waste read time after the reading of the alarm signal content represents the time during which the computer can do no useful work but waste the time, and the essential traffic control will be greatly affected adversely. While it is possible to use a computer designed so that the computer detects the number of alarm signals stored in the memory circuit so as to read only the stored alarm signals, this is also disadvantageous in that a certain time is required to detect the number of alarm signals stored and also the use of a complex program is required.